1. Field of the Invention
The present invention relates to synchronous detectors using block phase estimators. In particular, the invention relates to a phase averager of a block phase estimator.
2. Description of Related Art
Differential demodulator technology is often selected for a burst demodulator. A differential demodulator locks on to the carrier instantly; however, it has degraded performance in presence of noise. A coherent demodulator, where the carrier is coherently regenerated using a filter or phase locked loop, will theoretically provide superior noise performance if the loop bandwidth is narrow relative to the symbol rate; however, it is comparatively slow to lock on to the carrier. In the case of a phase locked loop, the lock on time is further increased by a hang-up phenomenon.
A block phase estimator is an alternative to the phase locked loop. The block phase estimator provides performance similar to the phase lock loop but does not suffer from the hang-up phenomenon.
In FIG. 1, digital receiver 10 includes an antenna coupled to a receiver. The receiver's output from its IF final stage is provided to in-phase and quadrature mixers. A local oscillator, using a Hilbert (.pi./2) transformer, provides in-phase and quadrature phase reference signals to the mixers. The mixer outputs are analog in-phase signal I and analog quadrature phase signal Q. The voltage V at the output of the final IF stage is given by EQU V=I+jQ,
where j is the complex operator. Analog signals I,Q are sampled in analog to digital converters, filtered, decimated and interpolated to produce digitally sampled signals I.sub.i and Q.sub.i. The filter is preferably a Nyquest filter matched to the modulation expected. The decimator/interpolator down samples the samples from the analog to digital converter to the symbol rate and resamples the signal at the center of each symbol.
In operation, when the antenna receives a continuous wave signal at a fixed, non-varying frequency to which the oscillator is precisely tuned in frequency and synchronized in phase, the outputs I.sub.i, Q.sub.i from digital receiver 10 do not vary with time. However, if the oscillator is tuned to a frequency other than the exact frequency of the signal being received, outputs I.sub.i, Q.sub.i will vary with time. The phase of the filtered/decimated/interpolated voltage V.sub.i is represented by the arctangent of the ratio of Q.sub.i to I.sub.i. This phase angle variation over time corresponds to the frequency difference between the oscillator's characteristic frequency and the frequency of the signal received at the antenna. Conventional phase-locked loop synchronous detectors measure this phase difference, filter the measured difference, and use this filtered phase difference to control the frequency of the local oscillator (i.e., a voltage controlled oscillator). However, the present invention relates to a block phase estimator as an alternative technology to phase-locked loops.
A constant frequency received by digital receiver 10 has little or no utility since it carries no information. In useful communication systems, signals received by the antenna include modulation. The present invention relates to a block phase estimator used in a decoder for decoding phase shift keying (PSK).
FIG. 2 is a graph depicting locations of voltage V from digital receiver 10 receiving a QPSK (quadrature phase shift keying) signal as received by both conventional decoders and a decoder according to the present invention. Signals I.sub.i, Q.sub.i may be plotted on the graph of FIG. 2. In a QPSK signal, a symbol may take on one of four values depicted in FIG. 2 as -135.degree.-45.degree.+45.degree.+135.degree.. The object of a decoder is to determine which phase is being transmitted during the duration of the symbol.
In FIG. 6, conventional decoder 60 includes block phase estimator 50, and block phase estimator 50 includes modulation removal circuit 20, averager 30 and phase corrector tracker 40.
FIG. 3 depicts modulation removal circuit 20. Modulation removal circuit 20 includes Cartesian to polar transformer 22, multiplier 24 and a polar to Cartesian transformer made from a cosine transformer 26 and a sine transformer 28. In FIG. 3, digital sample signals I.sub.i, Q.sub.i from digital receiver 10 (FIG. 1) are converted to polar coordinates using an arctangent function to provide a phase estimate of the phase of the current sample. The phase estimate of the phase of the current sample is phase .phi..sub.i. Multiplier 24 multiplies phase .phi..sub.i by M, where M is the number of phases encoded into the PSK signal. This provides a phase estimate of the current sample with modulation removed. For BPSK signals, M is 2; for QPSK signals, M is 4; for 8-PSK signals, M is 8; etc. FIG. 2 depicts four phases so that M would equal 4; however, M may advantageously be 8, 16, etc. The output of multiplier 24 is converted back into Cartesian coordinates by cosine transformer 26 and sine transformer 28 to provide signals I.sub.i ', Q.sub.i '. It should be noted here that the output of mulitplier 24 may include phase angles greater than 2.pi. radians; however, transformers 26, 28 are cyclical in nature and the outputs of these transformers are uneffected by angles greater than 2.pi. radians.
The operation of modulation removal circuit 20 is best understood in connection with FIG. 2. The four locations depicted in FIG. 2 as possible voltages from receiver 10 will become multiplied in multiplier 24 by four (4) since the signals depicted in FIG. 2 are quadrature PSK signals. For example, the 45.degree. phase depicted in the first quadrant in FIG. 2, when multiplied by 4 becomes 180.degree.. Similarly the -45.degree. when multiplied by four becomes -180.degree.. When multiplied by four, the 135.degree. phase angle becomes 540.degree. (i.e., 180.degree.+360.degree.). Similarly the -135.degree. becomes -540.degree.. Since cosine and sine transformers 26, 28 cyclically repeat, all phases output of multiplier 24 created from any one of the signal locations depicted in FIG. 2 will be interpreted as having a phase angle of 180.degree.. Thus, modulation is removed by modulation removal circuit 20.
However, if the oscilator in FIG. 1 does not exactly replicate the frequency of the carrier signal received from the antenna, the constellation of four locations depicted in FIG. 2 will rotate with time, either counter clock wise or clock wise depending on the sign of the frequency deviation. It is this frequency deviation that is measured in the block phase estimator. If there is a small frequency deviation, the phase output of multiplier 24 will be different than 180.degree..
FIG. 4 depicts conventional averager 30 as having two separate averaging circuits 32. Each averaging circuit 32 provides average signals I.sub.AVG ', Q.sub.AVG ' by maintaining a moving average of the input signals I.sub.i ' Q.sub.i '. The averaging is carried out, preferably, over a duration of time corresponding to several symbols. The sampling rate of the A to D converters in FIG. 1 is higher than the symbol rate. For example, the analog to digital converters may provide four samples over a symbol duration, and averaging circuits 32 would average the values input to these circuits by adding the values from sixteen samples and dividing by sixteen or scaling appropriately (e.g., four samples with four samples per symbol).
In FIG. 5, phase corrector tracker 40 includes Cartesian to polar transformer 42 (similar to Cartesian to polar transformer 22 in FIG. 3), divider 44, sector tracker 46, and polar to Cartesian transformer 48 (similar to the polar to Cartesian transformer 26, 28 of FIG. 3). Divider circuit 44 merely divides the phase input thereto (i.e., .phi..sub.AVG ') by M to provide the signal input to the sector tracker.
Divider 44 restores the phase value that was multiplied in multiplier 24 of FIG. 3; however, the range over which the phase output of divider 44 may vary is limited to 360.degree..div.M. In order to ensure correct restoration of the average phase, sector tracker 46 adds or subtracts a phase angle defined by 360.degree..div.M whenever it detects that the phase output of divider 44 jumps sharply. The output of sector tracker 46 is then converted to Cartesian coordinates in transformer 48.
The output of block phase estimator 50 (FIG. 6) contains Cartesian values for I, Q with the modulation removed but averaged over the averaging interval (e.g., 4 symbols). The output of block phase estimator 50 is estimated reference signals I.sub.EST, Q.sub.EST. In order to best provide for detection of signals against this average, it is necessary to delay those signals. Signals I.sub.i, Q.sub.i are delayed in delay circuits 52 to provide delayed signals I.sub.DEL, Q.sub.DEL. The delay duration can be chosen to use prior symbols, post symbols, or a combination of both. De-rotator 54 is a full complex by complex multiplier to form the product of delayed incoming data signal I.sub.DEL, Q.sub.DEL with reference signal I.sub.EST, Q.sub.EST. The output of de-rotator 54 is passed to decision devices 56. The in-phase decision device output value indicates whether the voltage being detected is in the left or right half plane of the plane depicted in FIG. 2, and the quadrature decision device output value indicates whether the voltage being detected is in the upper or lower half plane of FIG. 2. Decision devices 56 may include two comparators to determine which half plane the I value is in and which half plane the Q value is in.